With the increase in the degree of integration of semiconductor devices, a technique for the planarization of an insulating layer formed over a semiconductor wafer or substrate is further required to assure the photolithographic process margin and to minimize the length of a metal interconnection. In order to planarize an insulating layer, particularly an interlayer insulating layer, several methods have been used. Some examples include: a method for reflowing a doped glass such as BPSG (Boro-Phospho-Silicate-Glass), a SOG (Spin On Glass) process, an etch back process to be performed after depositing a photoresist on the insulating layer, a CMP (Chemical Mechanical Polishing) process for planarizing a deposited insulating layer, and the like. Of these methods, the CMP process allows low-temperature planarization, which can not be achieved by reflowing process or etch back process. Therefore, the CMP process has come into wide use in substrate planarization.
A conventional method for manufacturing a semiconductor device having a DRAM (Dynamic Random Access Memory) cell region and a logic region will now be described with reference to FIG. 1.
Referring to FIG. 1, a transistor including a gate 12 is first formed over a semiconductor substrate 10, whose device isolation is defined by a field oxide 11. A capacitor 14 is formed in direct contact with the substrate 10, and is insulated from the gate 12 by a sidewall spacer 13a and a capping insulating layer 13b which are formed over or beside the gate 12.
Next, an insulator deposition and CMP process is performed to form a first insulating layer 15 having a planarized surface. After forming a contact hole through the planarized insulating layer 15, a first tungsten plug 16a is formed to fill the contact hole and then a first interconnection 17a is formed in electrical contact with the first tungsten it plug 16a.
Subsequently, the insulator deposition and CMP process and the plug and interconnection forming processes are again performed to form a second tungsten plug 16b through a second insulating layer 18 and to form a second interconnection 17b on the second tungsten plug 16b.
As described immediately above, since the field oxide 11 and the gate 12 are simultaneously formed in the DRAM cell region and the logic region before the formation of the capacitors, a high step between devices is not generated. After the formation of the capacitors, however, since the capacitor 14 is formed in the DRAM cell region only, a step between the DRAM cell region and the logic region is very high. Thus, when the insulating layer 15 is deposited after the formation of the capacitor 15, the above-mentioned CMP process should be performed to obtain a flat surface for the insulating layer 15. This leads to one serious problem in that a dishing phenomenon, which results from the uneven polishing by a polishing pad caused by a pressure difference between a portion of the substrate in direct contact with the polishing pad and the other surfaces of the substrate.
To suppress the dishing phenomenon, two polishing steps are used: an etch back step using a photoresist and a CMP step. First, the etch back process using photoresist is performed to remove a constant amount of the insulating layer in a high step region. Then, the CMP process is performed to planarize an overall surface of the substrate.
However, this method has two disadvantages. One disadvantage is that yield is reduced because of the increased number of steps in substrate planarization. The other disadvantage is that this process generates a large number of particles during the polishing because of the etch back using the photoresist.